The present invention relates to a semiconductor device, in particular, to a technique effective to be applied to a semiconductor device with a semiconductor chip, having bonding pads, mounted thereon.
Japanese Patent Laid-Open No. 1991-79055 (Patent Document 1), for example, discloses an electrode pad provided with a first portion to bond a wire or a film lead and a second portion that is integrally linked to the first portion, can be recognized with a pattern distinct from the first portion, and makes contact with a probe needle in wafer testing.
Japanese Patent Laid-Open No. 2000-164620 (Patent Document 2) discloses a technique capable of secure inspection and bonding of a semiconductor device by having an electrode pad provided with an electrode region for bonding and a bonding region for inspection and separating the center of the electrode region for bonding and the center of the bonding region for inspection by a predetermined interval or more.
Japanese Patent Laid-Open No. 2001-338955 (Patent Document 3) discloses a wire bonding technique in which a bonding pad is provided with a bonding region and a probe contact region, where one end of a conductive wire is bonded to the bonding region and a tip end of a testing probe is made contact with the probe contact region.
Japanese Patent Laid-Open No. 2007-318014 (Patent Document 4) discloses a semiconductor device in which a plurality of pads having a first region and a second region are formed in a rectangular shape, where each pad has a chamfered portion in a part of the corners and the pads are aligned in zigzag and further the chamfered portions are provided oppositely in the pads in inner and outer rows of the zigzag alignment and the first region is disposed on the side of the core logic region of a semiconductor chip.